Verilog - inout bus for TestBench

source code
D=(RD==0)?Dout:8'hZ;
TestBench
D=(WR==0)?Din:8'hZ;

http://www.inno-logic.com/tech-forum/viewtopic.php?p=172&sid=1c0d3d986db2d60b23201d258fcce985

I am having trouble writing data to a bi-directional port. I basically have a module with an inout port .
inout [7:0] ioMpData;

TestBench is
wire [7:0] ioMpData;
You have declared ioMpData, a bidrectional bus as wire. Now you use assign statmenet to assign values to this, when it is input else assign high-z.

assign ioMpData = (IN_MODE == 1) ? IN1[7:0] : 8'hz;

This aasigns IN1 to the io bus during inmode else puts in high impedence state.


module t;
reg [15:11] A;
reg WR;
reg RD;
reg PSEN;
reg ALE;
wire [7:0] D; //Bus//
...
reg Din;
reg Dout;

main m (.A(A),.WR(WR),.RD(RD),.PSEN(PSEN),.ALE(ALE),.D(D),...); //inout [7:0] D;//

// Enter fixture code here
assign #0 D=(WRDBus==0)?Din:8'hZ;
initial begin
...
end
always begin
...
end
endmodule // t

http://www.asic-world.com/verilog/assertions2.html

Ram Model